The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for reducing through process delay variation in metal wires.
Optical lithography is a crucial step in semiconductor manufacturing. The basic principle of optical lithography is quite similar to that of chemistry-based photography. The images of the patterned photo-mask are projected through the high-precision optical system onto the wafer surface, which is coated with a layer of light-sensitive chemical compound, e.g. photo-resist. The patterns are then formed on the wafer surface after complex chemical reactions and follow-on manufacturing steps, such as development, post-exposure bake, and wet or dry etching.
Due to the unavoidable diffraction, the optical lithography system is lossy in the sense that only low frequency components of the electromagnetic field can pass the optical system. Given a target layout of shapes that are desired to be manufactured, masks are generated that account for the non-linearities introduced by the lithographic process that prints wafer features that resemble the target. As the gap between the required feature size and lithography wavelength gets bigger, the final wafer images are quite different from the patterns on the mask. In the past few years, resolution enhancement techniques (RETs) have become necessary in order to achieve the required pattern density. One well-known RET is the optical proximity correction (OPC), in which the mask patterns are intentionally “distorted” so that the desired image can be formed on the wafer. Other commonly used RETs are sub-wavelength resolution assist features (SRAF) and phase-shift masks (PSM). Nowadays, considerable amount of computing power has to be dedicated to these post-layout processes (often referred as data prep).
Optical proximity correction OPC involves simulating the wafer image given a mask. OPC extracts the geometric error between the simulated wafer feature and the target. The geometric error is called edge placement error (EPE). A cost function is defined as the summation of the EPEs across a layout and modifications of the mask are performed so as to minimize this cost function. OPC arrives at a final mask solution after several iterations of image simulations and mask modifications. One drawback of this type of mask modification is that the image simulation is performed at a single process point, most often under nominal process conditions. Hence, OPC cannot compensate for any variations that may occur during the lithographic process such as variations in lithographic dose and focus.
Lithographic variations in dose, focus, etc. degrade image quality across the process window. Variations appear in the form of process variability bands (PV-bands) and lead to variability in electrical metrics. For example, metal wires experience resistance/capacitance delay.
In nanometer scale technologies, wafer structures show an increased susceptibility to lithographic variations. This often leads to fails such as shorts and opens of electrical structures, thus also limiting wafer yield. In order to improve yield, a method known as retargeting is employed in current processes. Retargeting is the procedure of modifying target layout shapes prior to handing it off to mask making tool (OPC). Modifying target layout shapes can make layouts more robust to process variability and hence reduce electrical fails. However, it also modifies the electrical properties of the circuit itself, which is often not accounted for during the retargeting process.